Semiconductor device, operation method of semiconductor device, and manufacturing method of semiconductor device
US10629618B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 8, 2017 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Sep 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/966
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present disclosure relates to a semiconductor device, an operation method of a semiconductor device, and a manufacturing method of a semiconductor device which are capable of minimizing influence of a gate length variation on a circuit characteristic and increasing a good product ratio (yield) in a product sorting test. A ring oscillator configured such that the plurality of inverters is connected in a ring-like form, and gate capacitors of the transistors are connected to respective output terminals of the plurality of inverters as a load capacitor outputs an oscillating signal, the ring oscillator is configured with a plurality of transistors having the same gate length, and at least two or more ring oscillators including a plurality of transistors having different gate lengths are configured. At the time of product test, the gate length is calculated on the basis of frequencies of oscillating signals of a plurality of ring oscillators, and a back bias is applied in accordance with a correction value corresponding to the calculated gate length, and an operation is performed. The present disclosure can be applied to semiconductor devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.