Cell architecture based on multi-gate vertical field effect transistor
US10629682B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 25, 2019 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Jan 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
A cell architecture is provided. A cell architecture including a vertical field effect transistor (VFET) having at least two fins serving as a vertical channel, a gate including a first gate portion surrounding the first fin, a second gate portion surrounding the second fin, and a third gate portion providing connection therebetween, and a top source/drain (S/D) including a first top S/D portion on the first fin and a second top S/D portion on the second fin, a gate contact structure connected to the third gate portion, a top S/D contact structure connected to one of the first top S/D portion or the second top S/D portion and serving as a horizontal conductive routing layer; and metal patterns on the gate contact structure and the top S/D contact structure and connected thereto through vias, and serving as a vertical conductive routing layer may be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.