Array substrate and manufacturing method thereof
US10629746B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 21, 2017 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Jan 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6723
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure discloses an array substrate and manufacturing method thereof. The method includes: forming a gate layer on the surface of a substrate; forming an insulating layer on the surface of the gate layer; forming a polysilicon layer having a separating portion on the surface of the insulating layer; and forming a source drain layer on the surface the polysilicon layer having the separating portion, such that the source drain layer is not directly in contact with the polysilicon layer. Through the above-mentioned method, the contact resistance of the source drain layer and the amorphous silicon layer is effectively improved, thereby effectively reducing the leakage current, and the characteristic of TFT device is greatly improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.