Split-gate flash memory cell and method for forming the same
US10629753B2 · kind B2 · utility
1Cited by
7References
20Claims
0Family size
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Key dates
| Filing date | Dec 12, 2017 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Dec 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/661
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A split-gate flash memory cell is provided. The split-gate flash memory cell includes a semiconductor substrate, a floating gate dielectric on the semiconductor substrate, and a floating gate. The floating gate includes a conductive layer on the floating gate dielectric, and a pair of conductive spacers on a top surface of the conductive layer. The split-gate flash memory cell also includes an inter-gate dielectric covering the floating gate, including sidewalls of the conductive layer and the conductive spacers. The split-gate flash memory cell also includes a control gate on the inter-gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.