Clock circuit having a pulse width adjustment module
US10630273B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2019 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Apr 24, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock circuit has a clock input terminal, a first clock output terminal, and a second clock output terminal. The clock circuit includes a pulse width adjustment module, a sampling module, a comparing module, and a differential signal converting module. A differential input terminal is electrically connected to a pulse width output terminal of the pulse width adjustment module. A positive differential signal output terminal and a negative differential signal output terminal are electrically connected to the first clock output terminal of the clock circuit and the second clock output terminal to output two clock signals with a phase difference of 180 degrees, respectively. A second input terminal of the sampling module is electrically connected to the second clock output terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.