Patent · US Active

Method for biasing outputs of a folded cascode stage in a comparator and corresponding comparator

US10630274B2 · kind B2 · utility

1Cited by

4References

20Claims

0Family size

Assignee

STMicroelectronics (Rousset) SAS · FR

Inventors

Yohan Joly · Le Tholonet, FR
Vincent Binet · Les Granettes, FR

Key dates

Filing date	Jun 24, 2019
Grant date	Apr 21, 2020
Priority date	—
Expiry date	Jun 24, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH03F2203/45
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A comparator includes a folded cascode stage having positive and negative outputs. The folded cascode stage includes: a common-mode voltage regulation circuit that includes resistive elements that are respectively situated between each of the outputs and a common-mode node. A compensation circuit is configured to regulate a difference between the voltages on the outputs, and is configured to generate a constant and continuous compensation current in the two resistive elements. A hysteresis circuit is configured to offset voltages on the outputs, and to generate a hysteresis current in the two resistive elements.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.