Sub-ranging analog-to-digital converter
US10630304B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2019 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Apr 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sub-ranging analog-to-digital converter (ADC) converts an analog input signal to a digital output signal. The sub-ranging ADC includes a coarse ADC, a fine ADC, and an error correction circuit (ECC). The fine ADC includes at least three digital-to-analog converters (DACs) that are connected in a pipeline architecture. The coarse and fine ADCs receive the analog input signal in a first half cycle of a clock signal. The coarse ADC converts the analog input signal to a first digital signal in a second half cycle of the clock signal. At least one of the first through third DACs converts the analog input signal to a second digital signal in a full cycle of the clock signal. The ECC receives the first and second digital signals and generates the digital output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.