Optimized arrays for segmented successive-approximation-register (SAR) analog-to-digital converter (ADC)
US10630307B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2019 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Sep 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including a segmented successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitive structure with a first plurality of capacitive structure subcomponents that each include a first terminal selectively connected to one of a plurality of input voltage nodes and a second terminal connected to a common conductor, and second capacitive structure with a second plurality of capacitive structure subcomponents that each include a first terminal selectively connected to one of the plurality of input voltage nodes and a second terminal connected to the common conductor. The first and second plurality of capacitive structure subcomponents are arranged in an array in which none of the first plurality of capacitive structure subcomponents are directly adjacent to one another and none of the second plurality of capacitive structure subcomponents are directly adjacent to one another in a first row in the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.