Analog signal generation by hardware re-use in sampled circuits
US10630310B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2019 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Jul 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated charge redistribution successive approximate register (CR-SAR) analog-to-digital converter (ADC) includes a sample-and-hold switch, a digital-to-analog converter (DAC), a comparator and a logic circuit. The sample-and-hold switch obtains a sample input voltage (Vin). The DAC includes a plurality of digital multiplexers that selects between a superposition phase, which superimposes an analog offset voltage onto Vin, and a conversion phase which determines values for a digital output register which determines the input values to each control line. Each digital multiplexer presents input values to a control line. The comparator has two inputs coupled to the sample-and-hold switch and to the DAC such that the output of the converter determines a value of each successive bit in the digital output register. The logic circuit is coupled to the comparator and to digital multiplexers and includes the digital output register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.