Structure of interleaver with LDPC code
US10630319B2 · kind B2 · utility
1Cited by
8References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 23, 2018 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Apr 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Concepts and schemes pertaining to structure of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide encoded data. A transceiver of the apparatus transmits the encoded data to at least one network node of a wireless network. In encoding the data to provide the encoded data, the processor encodes the data to result in each code block in the encoded data comprising a respective bit-level interleaver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.