Architecture and instruction set to support interruptible floating point division
US10635395B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2016 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Oct 6, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4873
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor (and method) includes a core that performs a floating point division through execution of various instructions. The instructions include a sign, exponent, and mantissa (SEM) separation instruction which causes the core to extract the sign, exponent and mantissa values from numerator and denominator floating point numbers. The instructions also include an unsigned mantissa division instruction which cause the core to iteratively perform a conditional subtraction operation to compute a value indicative of a mantissa of the quotient. The instructions further include a merge instruction that causes the core to generate a quotient floating point number using the extracted sign and exponent from the SEM separation instruction and the value indicative of the mantissa of the quotient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.