Memory pool allocation for a multi-core system
US10635494B2 · kind B2 · utility
0Cited by
4References
14Claims
0Family size
Assignee
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Key dates
| Filing date | May 8, 2018 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Aug 16, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5011
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes processing cores, memory blocks, a connection between each of processing core and memory block, chip selection circuit, and chip selection circuit busses between the chip selection circuit and each of the memory blocks. Each memory block includes a data port and a memory check port. The chip selection circuit is configured to enable writing data from a highest priority core through respective data ports of the memory blocks. The chip selection circuit is further configured to enable writing data from other cores through respective memory check ports of the memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.