Detecting bus faults
US10635518B2 · kind B2 · utility
0Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2017 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Mar 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/40273
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique includes monitoring a sequence of bits of data communicated to a transmitter of a node, where the transmitter communicates signals with a bus in response to the sequence of bits. The technique includes determining whether the sequence of bits represents acknowledgement by the node that data was received from the bus in an associated data frame and represents detection by the node of an error associated with the data frame. The technique includes detecting a fault associated with the bus based on the result of the determination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.