Core utilization optimization by dividing computational blocks across cores
US10635969B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2016 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Feb 28, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/049
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Core utilization optimization by dividing computational blocks across neurosynaptic cores is provided. In some embodiments, a neural network description describing a neural network is read. The neural network comprises a plurality of functional units on a plurality of cores. A functional unit is selected from the plurality of functional units. The functional unit is divided into a plurality of subunits. The plurality of subunits are connected to the neural network in place of the functional unit. The plurality of functional units and the plurality of subunits are reallocated between the plurality of cores. One or more unused cores are removed from the plurality of cores. An optimized neural network description is written based on the reallocation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.