Memory cell for computing-in-memory applications, memory unit for computing-in-memory applications and computing method thereof
US10636481B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2019 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | May 13, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell for computing-in-memory applications is controlled by a first bit line, a second bit line, a word line and a read word line. The read word line transmits an input value. The memory cell includes a plurality of read-decoupled cells. Each of the read-decoupled cells stores a weight and includes a first read-decoupled transistor and a second read-decoupled transistor. The first read-decoupled transistor has a first transistor width and is controlled by the weight. The second read-decoupled transistor has a second transistor width equal to the first transistor width and generates a read bit line signal according to the input value, the weight and the second transistor width. The second transistor width of the second read-decoupled transistor of one of the read-decoupled cells is two times larger than the second transistor width of the second read-decoupled transistor of another one of the read-decoupled cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.