Method for alignment, process tool and method for wafer-level alignment
US10636688B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2018 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Jun 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/80948
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.