Apparatus and method for ensuring reliability of trip protection of intelligent substation
US10637287B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 14, 2016 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Jun 2, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY04S40/124
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for ensuring the reliability of a trip protection of an intelligent substation. The apparatus comprises a main CPU and an auxiliary CPU connected together, and a main FPGA and an auxiliary FPGA connected together. The main FPGA and the auxiliary FPGA are connected to a physical layer of a protection apparatus, and the main CPU and the auxiliary CPU are connected to a state monitoring data output end of a protected device. The main CPU sends a processing result to the main FPGA, the auxiliary CPU sends the processing result to the auxiliary FPGA, and the auxiliary FPGA synchronizes current information with the main FPGA after receiving information sent by the auxiliary CPU. When the main FPGA receives trip information, the main FPGA comparing the consistency of current trip information obtained from the main CPU with current trip information obtained from the auxiliary FPGA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.