Dead-time control for half-bridge driver circuit
US10637348B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 10, 2019 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Jun 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0072
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A gate driver circuit includes an input terminal for receiving an input switching signal for driving a switching circuit that has a high-side transistor and a low-side transistor vertically stacked. The gate driver circuit also includes a dead-time control circuit, that includes two dead-time measurement circuits. The first dead-time measurement circuit produces a first pulse signal having a first pulse width representing a first dead-time between when a gate voltage of the low-side transistor falls below a first threshold voltage and when a gate voltage of the high-side transistor rises above a second threshold voltage. The second dead-time measurement circuit produces a second pulse signal having a second pulse width representing a second dead-time between when the gate voltage of the high-side transistor falls below the second threshold voltage and when the gate voltage of the low-side transistor rises above the second threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.