Apparatus and method for accelerating multiplication with non-zero packets in artificial neuron
US10637500B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2018 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Dec 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An acceleration apparatus applied in an artificial neuron is disclosed. The acceleration apparatus comprises an AND gate array, a first storage device, a second storage device and a multiply-accumulate (MAC) circuit. The AND gate array with plural AND gates receives a first bitmap and a second bitmap to generate an output bitmap. The first storage device stores a first payload and outputs a corresponding non-zero first element according to a first access address associated with a result of comparing the first bitmap with the output bitmap. The second storage device stores a second payload and outputs a corresponding non-zero second element according to a second access address associated with a result of comparing the second bitmap with the output bitmap. The MAC circuit calculates a dot product of two element sequences from the first storage device and the second storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.