Routing topology for digital signals with resistive combiners for reduced jitter
US10637801B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2018 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Aug 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9023
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A signal routing circuit is disclosed which employs resistive combiners to reduce signal jitter. A signal routing circuit configured according to an embodiment comprises an input stage including a plurality of buffer circuits. Each of the buffer circuits is controlled by a selection signal to enable an input signal at an input port of the buffer circuit to generate an output signal at an output port of the buffer circuit. The signal routing circuit also includes a plurality of resistors to couple the output port of each of the buffer circuits of the input stage to a summing junction. The signal routing circuit further includes an output stage including an additional buffer circuit. The input port of the additional buffer circuit is coupled to the summing junction, and the output port of the additional buffer circuit is configured to provide the routed output signal based on the selection signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.