Wear leveling in solid state devices
US10642495B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Jul 9, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a memory-efficient mechanism for identifying memory blocks with a low wear count. More particularly, embodiments of the present disclosure provide a mechanism for identifying a memory block whose wear count is within the bottom p % of all wear counts associated with memory blocks in a storage system. If a memory controller performs the garbage collection operation on a memory block whose wear count is within the bottom p % of all wear counts, then the memory controller is expected to utilize the remaining memory blocks (e.g., memory blocks whose wear count is within the upper (100−p) % of all wear counts) efficiently and level the wear count of at least the remaining memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.