Process of programming field programmable gate arrays using partial reconfiguration
US10642630B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Nov 15, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a method is disclosed providing an improvement in speed and efficiency of programming field programmable gate array (FPGA) digital electronic integrated circuits (ICs) or other ICs that support partial reconfiguration, a particular FPGA having a plurality of reconfigurable partitions and a plurality of primitive variations configurable in each of the reconfigurable partitions, the method comprising: before writing configuration bitstreams to the particular FPGA, compiling and storing, using digital storage, a plurality of primitive bitstreams for a plurality of different primitive functions that can be written to and implemented on the particular FPGA; receiving input in a graphical user interface to select and connect graphical blocks representing functional logic of an algorithm to implement on the particular FPGA, the graphical blocks relating to reconfigurable logic; automatically determining a subset of the primitive functions comprising particular primitive functions that correspond to the graphical blocks; obtaining, from the digital storage, a subset of the primitive bitstreams that corresponds to the subset of the primitive functions; using one or more pa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.