System and method for memory interface load balancing
US10642733B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Jul 12, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and a method of balancing a load of access of at least one computing device to an arbitrary integer number of connected memory devices associated with a memory cluster address space, the method including: determining, by a controller, a number N corresponding to an arbitrary integer number of memory devices connected to a plurality of memory interfaces, wherein N is between 1 and the number of memory interfaces; receiving, by the controller, at least one data object, corresponding to an original processor address (OPA) from the at least one computing device; computing, by the controller, at least one interleaving function according to N; and mapping, by an interleaving circuit, the OPA to a memory cluster address (MCA), according to the at least one interleaving function, so that the data object is equally interleaved among the N connected devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.