Patent · US Active

Key invalidation in cache systems

US10642745B2 · kind B2 · utility

1Cited by
16References
20Claims
0Family size

Assignee

Inventor

Key dates

Filing dateJan 4, 2018
Grant dateMay 5, 2020
Priority date
Expiry dateJul 21, 2038

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F2212/608
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Techniques are disclosed relating to invalidating keys in a cache. In some embodiments, a computer system may implement a cache for a data store, where the cache stores a data set and is organized such that a stored data item of the data set is specified by a corresponding key having one or more portions. The computer system may store metadata for the cache, where the metadata includes nodes organized in a hierarchy. The computer system may receive a request to invalidate one or more keys of the cache, and may invalidate a particular node within the metadata based on a key value corresponding to the request.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.