Efficient signaling scheme for high-speed ultra short reach interfaces
US10642767B1 · kind B1 · utility
21Cited by
9References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 24, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Aug 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15192
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A master integrated circuit (IC) chip includes transmit circuitry and receiver circuitry. The transmit circuitry includes a timing signal generation circuit to generate a first timing signal, and a driver to transmit first data in response to the first timing signal. A timing signal path routes the first timing signal in a source synchronous manner with the first data. The receiver circuitry includes a receiver to receive second data from a slave IC chip, and sampling circuitry to sample the second data in response to a second timing signal that is derived from the first timing signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.