Serial peripheral interface daisy chain mode system and apparatus
US10642769B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2017 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Apr 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
SPI frame for simultaneously entering 8 bit daisy-chain mode from 16 bit register addressable mode. Some products that implement SPI may be connected in a daisy chain configuration, the first slave output being connected to the second slave input, etc. The SPI port of each slave is designed to send out during the second group of clock pulses an exact copy of the data it received during the first group of clock pulses. The whole chain acts as a communication shift register; daisy chaining is often done with shift registers to provide a bank of inputs or outputs through SPI. Large latency occurs during the entry into daisy-chain mode which increases as a function of the number of linked SPI devices. A means for simultaneously instructing all connected devices to enter/enable daisy-chain mode is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.