Tie-high and tie-low circuits
US10643013B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 21, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | May 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/911
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A tie-high circuit includes: a p-type metal-oxide-semiconductor (PMOS) transistor connected to a power rail in a standard cell library; and a decoupling capacitor connected to a ground rail in the standard cell library and the PMOS transistor. The decoupling capacitor includes an n-type metal-oxide-semiconductor (NMOS) transistor having either one of a source and a drain of the NMOS transistor being connected to the ground rail via an active resistor. A tie-low circuit includes: an n-type metal-oxide-semiconductor (NMOS) transistor connected to a ground rail in a standard cell library; and a decoupling capacitor connected to a power rail in the standard cell library and the NMOS transistor. The decoupling capacitor of the tie-low circuit includes a PMOS transistor having either one of a source and a drain of the PMOS transistor being connected to the power rail via an active resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.