Method for fabricating laterally insulated integrated circuit chips
US10643856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Sep 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/3341
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Laterally insulated integrated circuit chips are fabricated from a semiconductor wafer. Peripheral trenches are formed in the wafer which laterally delimit integrated circuit chips to be formed. A depth of the peripheral trenches is greater than or equal to a desired final thickness of the integrated circuit chips. The peripheral trenches are formed by a process which repeats successive steps of a) ion etching using a sulfur hexafluoride plasma, and b) passivating using an octafluorocyclobutane plasma. Upon completion of the step of forming the peripheral trenches, lateral walls of the peripheral trenches are covered by an insulating layer of a polyfluoroethene. A thinning step is performed on the lower surface of the wafer until a bottom of the peripheral trenches is reached. The insulating layer is not removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.