Method for producing at least one via in a wafer

US10643896B2 · kind B2 · utility

Assignee

• Robert Bosch GmbH · DE

Inventors

• Heiko Stahl · Reutlingen, DE
• Jochen Reinmuth · Reutlingen, DE
• Markus Kuhnke · Wannweil, DE
• Stefan Majoni · Holzgerlingen, DE
• Timo Schary · Grötzingen, DE

Key dates

• Filing date: Sep 19, 2018
• Grant date: May 5, 2020
• Expiry date: Nov 15, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L23/481
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for producing a via in a wafer includes providing a wafer, comprising silicon. The method includes producing a conductive region, in the form of a conductor track, preferably composed of polycrystalline silicon, in the wafer. The method includes producing a hole in the wafer such that the hole is fluidically connected to the conductive region and the sidewalls of the hole comprise silicon. The method includes applying a tungsten hexafluoride-resistant protective layer, produced from silicon oxide, in the region of the surface of the hole that is to be produced or has been produced, such that an opening of the hole is free of a protective layer. The method includes applying tungsten hexafluoride to the hole and the region of the opening of the hole by a reducing-agent-free vapor phase deposition process, preferably in the form of a CVD process, for producing the via.