Semiconductor fabrication method thereof
US10643963B2 · kind B2 · utility
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Key dates
| Filing date | Jun 20, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Jun 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/04941
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure and its fabrication method are provided. The fabrication method includes: providing a base substrate including a wiring region and an isolation region. A patterned layer is formed on the isolation region of the base substrate and the patterned layer exposes the wiring region of the base substrate. After forming the patterned layer, a redistribution layer is formed on the wiring region of the based substrate exposed by the patterned layer. A protective layer is formed on the redistribution layer, and after forming the protective layer, the patterned layer is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.