Semiconductor memory devices having bit line node contact between bit line and active region
US10644003B2 · kind B2 · utility
3Cited by
13References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 27, 2017 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Nov 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
Abstract
A semiconductor memory device includes a substrate having an active region, word lines extending across the active region, a bit line on the active region between the word lines, a bit line node contact between the bit line and the active region, and a storage node contact on an end portion of the active region, wherein one or more of the bit line node contact or the storage node contact include silicon germanium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.