Semiconductor device
US10644008B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Jul 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first bit line structure is disposed between a first contact structure and a second contact structure. A first air spacer is interposed between the first contact structure and the first bit line structure. A first separation space is connected to an air entrance of the first air spacer and interposed between the first contact structure and the first bit line structure. A cover insulating pattern with a gap portion is interposed between the first contact structure and the second contact structure. The gap portion has a downwardly-decreasing width. An air capping pattern covers the cover insulating pattern to seal the first separation space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.