Semiconductor modification process for conductive and modified electrical regions and related structures
US10644197B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2019 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Jan 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S5/2086
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
There is herein described a process for providing improved device performance and fabrication techniques for semiconductors. More particularly, the present invention relates to a process for forming features, such as pixels, on GaN semiconductors using a p-GaN modification and annealing process. The process also relates to a plasma and thermal anneal process which results in a p-GaN modified layer where the annealing simultaneously enables the formation of conductive p-GaN and modified p-GaN regions that behave in an n-like manner and block vertical current flow. The process also extends to Resonant-Cavity Light Emitting Diodes (RCLEDs), pixels with a variety of sizes and electrically insulating planar layer for electrical tracks and bond pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.