Array substrate, display panel and method for fabricating array substrate
US10644255B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Sep 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/80522
Abstract
The present disclosure relates to an array substrate, a method of fabricating the same, and a display panel. The array substrate includes a conductive layer formed on the base substrate, a dielectric layer formed on the conductive layer, wherein the dielectric layer has an opening exposing the conductive layer, wherein a vertical projection of the opening on the base substrate is in at least a portion of the pixel spacing region, a first electrode formed on the dielectric layer, a luminescent layer having a first portion on the first electrode and a second portion on the conductive layer in the opening, a second electrode formed on the luminescent layer, and an electrical connection portion in the second portion of the luminescent layer for providing an electrical connection from the conductive layer to the second electrode, and wherein the electrical connection portion is more conductive than the luminescent layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.