Voltage reference reconfiguration fault-tolerant control method for multi-level inverter
US10644611B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Oct 28, 2016 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | May 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/325
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a voltage reference reconfiguration fault-tolerant control method for a cascaded multi-level inverter. The fault-tolerant method for the inverter automatically reconfigures the three-phase voltage amplitudes and phases of the three-phase total voltage in accordance with the fault diagnosis, thus realizing three-phase voltage balance. On the basis of the reconfiguration of the total voltage signal, re-reconfiguration of reference voltage inputted into the various H-bridges is conducted in accordance with the fault signal vectors, thereby realizing removal of the fault bridges and fault-tolerance of the normal bridges, while guaranteeing the integral sinusoidal characteristics of the actual reference voltage. The inverter realized maximum three-phase balanced line voltage in a fault occurrence, has the advantages of requiring no redundant modules and algorithms and the advantages of ease of removing fault bridges, and is applicable for reduced load operable electrical equipment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.