Single-loop linear-exponential multi-bit incremental analog-to-digital converter
US10644718B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2019 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | May 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop for improving the signal to noise distortion ratio (SNDR) and the dynamic range (DR) is disclosed. The linear-exponential IADC includes an analog modulator and a decimation filter. The analog modulator has an input for receiving the analog input voltage and an output. The analog modulator includes an integrator, an adder, a quantizer, a noise-coupling path, a data weighted averaging (DWA) circuit, and a digital-to-analog converter (DAC). The decimation filter has an input for receiving signals from the output of the analog modulator. The decimation filter includes a 1st order accumulator, an exponential accumulator, and a decimator. The linear-exponential IADC is configured to operate with a linear phase for suppressing the thermal noise and an exponential phase for boosting the SQNR.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.