Array substrate with auxiliary gate metal pattern for common electrode connection and method for manufacturing the same, touch display panel and touch display device
US10649568B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 11, 2018 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Oct 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5226
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An array substrate and a method for manufacturing the same, a display panel and a display device are provided. The array substrate includes: a substrate; a gate metal layer arranged on the substrate, the gate metal layer including a gate line and a patterned auxiliary metal; a source and drain metal layer, the source and drain metal layer including source signal lines and touch signal lines, and the source and drain metal layer being separated from the gate metal layer by an insulating layer; a planarization layer arranged on the source and drain metal layer; and a common electrode arranged on the planarization layer. The patterned auxiliary metal is electrically connected to the touch signal lines through first holes penetrating the insulating layer, and is electrically connected to the common electrode through second holes penetrating the insulating layer and third holes penetrating the planarization layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.