Precise longitudinal monitoring of memory operations
US10649688B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2018 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Nov 10, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a memory subsystem having a first memory subunit that includes a status register and an execution engine unit coupled to the memory subsystem. The execution engine unit is to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit stores a piece of information, related to a status of the load operation, in the status register. Responsive to detection of retirement of the load operation, the first memory subunit is to store the piece of information from the status register into a particular field of a record of a memory buffer, wherein the particular field is associated with the first memory subunit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.