Logical block addressing range collision crawler
US10649909B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2018 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Sep 20, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device having a controller configured to execute a range crawler algorithm residing in firmware or hardware and a data table containing one or more range entries (RE's), where each of the RE's is part of a logical block address (LBA) span associated with a command instruction, and where each LBA span has one or more LBA ranges, and where each LBA range is made of one or more sequential LBA's. The device also includes a collision bitmap configured to store data associated with RE collisions between one or more LBA's and a command dispatcher configured to release selected LBA ranges that are not associated with a RE collision. The range crawler algorithm is configured to search the data table to detect collisions between the RE's.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.