Fin critical dimension loading optimization

US10651090B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Chia Ming Liang · Taipei, TW
• Yi-Shien Mor · Hsinchu, TW
• Huai-Hsien Chiu · Taipei, TW
• Chi-Hsin Chang · Taichung, TW
• Jin-Aun Ng · Hsinchu, TW
• Yi-Juei Lee · Hsinchu, TW

Key dates

• Filing date: Oct 31, 2017
• Grant date: May 12, 2020
• Expiry date: Oct 31, 2037

Classification

• Technology area (CPC —): General

Abstract

Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.