Semiconductor device and method of manufacturing the same
US10651277B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2019 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Mar 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D12/031
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.