Patent · US Active

Down-mode valley-current-sense replica linearization

US10651742B2 · kind B2 · utility

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19Claims

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Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Stefan Dietrich · Potsdam, DE
Joerg Kirchner · Enghausen, DE

Key dates

Filing date	Mar 5, 2019
Grant date	May 12, 2020
Priority date	—
Expiry date	Mar 5, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2217/0054
WIPO fieldElectrical machinery, apparatus, energy
WIPO sectorElectrical engineering

Abstract

A current measurement linearization circuit for a DC/DC boost converter includes a back-gate sensing transistor and a back-gate reset transistor. The back-gate sensing transistor has a first terminal coupled to a first body contact of a high-side power transistor and a second terminal coupled to a second body contact of a first replica transistor in a valley-current sensing circuit. The back-gate reset transistor has a first terminal coupled to a max reference voltage that is equal to the greater of an input voltage and an output voltage and a second terminal coupled to the second body contact.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.