Multiple chip synchronization via single pin monitoring of an external timing capacitor
US10651844B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2018 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Nov 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An IC chip, a system and a method of operating the IC chip in response to an event trigger are provided. The method includes responsive to the event trigger, coupling a pin to a source of constant current to charge an external capacitor coupled to the pin and monitoring a capacitor voltage on the pin. If the magnitude of the capacitor voltage is greater than a rising threshold, detection of a falling threshold is enabled. If the magnitude of the capacitor voltage is greater than a voltage threshold, a first response is triggered and the pin is coupled to the lower rail to discharge the external capacitor. If detection of the falling threshold is enabled and the magnitude of the capacitor voltage is less than the falling threshold, the first response is also triggered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.