Scalable packet processing
US10652162B2 · kind B2 · utility
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4References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2018 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Jul 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/20
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Particular embodiments described herein provide for an electronic device that includes at least one processor operating at eight hundred (800) megahertz and can be configured to receive a data stream, parse packets in the data stream, and process at least two (2) full packets from the data stream in a single clock cycle. In an example, the data stream is at least a two hundred (200) gigabit Ethernet data stream and a bus width is at least thirty-two (32) bytes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.