Power control for a dataflow processor
US10656911B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 11, 2019 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Feb 11, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for power conservation. A plurality of processing elements and a plurality of instructions are configured. The plurality of processing elements is controlled by instructions contained in a plurality of circular buffers. The plurality of processing elements can comprise a data flow processor. A first processing element, from the plurality of interconnected processing elements, is set into a sleep state by a first instruction from the plurality of instructions. The first processing element is woken from the sleep state as a result of valid data being presented to the first processing element. A subsection of the plurality of interconnected processing elements is also set into a sleep state based on the first processing element being set into a sleep state. At least one circular buffer from the plurality of circular buffers remains awake while the first processing element is in the sleep state, and the at least one circular buffer provides for data steering through a reconfigurable fabric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.