Technologies for demoting cache lines to shared cache
US10657056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Jun 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/622
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.