Latency test in networking system-on-chip verification

US10657217B2 · kind B2 · utility

Assignee

• MENTOR GRAPHICS CORPORATION · US

Inventors

• Suresh Krishnamurthy · Noida, IN
• Deepak Garg · Nashua, US
• Sudhanshu Jayaswal · Noida, IN
• Saurabh Khaitan · Noida, IN
• Sanjay Gupta · Crystal Lake, US
• John R. Stickley · Lake Oswego, US
• Russell Elias Vreeland, III · Henry's Drive, US
• Ronald James Squiers · Castro Valley, US
• Abhijit Das · Dallas, US
• Charles W. Selvidge · Waltham, US

Key dates

• Filing date: Oct 24, 2017
• Grant date: May 19, 2020
• Expiry date: Oct 24, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2115/02
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Aspects of the disclosed technology relate to techniques of latency test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates arrival time information with messages when the messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, and associates latency information with the messages when the messages are dispatched by the hardware model of the circuit design. The arrival time information of a particular message and the latency information are determined with respect to a model time reference provided in the reconfigurable hardware modeling device.