Route generation and buffer placement for disjointed power domains in an integrated circuit
US10657302B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Aug 4, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present embodiments relate to buffering signals between disjointed power domains with similar power profiles in an integrated circuit. According to some aspects, embodiments relate to a method in which an electronic design automation (EDA) tool displays a schematic including a plurality of first power domains having a first power profile and a plurality of second power domains having a second power profile. The EDA tool generates graph including a plurality of points and a plurality of edges connecting the points, where the points are located on the plurality of second power domains. The EDA tool selects one route from a plurality of routes from a start node on the graph to an end node on the graph and determines a number of buffers located on the route based on associated distance values and a design violation values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.