Gate driving circuit, method for driving the same, and display apparatus
US10657879B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 17, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Aug 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0247
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure disclose a gate driving circuit, a method for driving the same, and a display apparatus. The gate driving circuit includes N stages of cascaded shift registers, N being an integer greater than or equal to 4. In the N stages of shift registers, an output signal terminal of an nth stage of shift register is connected to an input signal terminal of an (n+I/2)th stage of shift register, and a reset signal terminal of the nth stage of shift register is connected to an output signal terminal of an (n+K)th stage of shift register, wherein n is an integer greater than or equal to 1 and less than (N−I/2), K is an integer greater than I/2 and less than I, and I is a number of clock signal lines connected to the gate driving circuit, which is an even number greater than or equal to 4.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.