Memory device with memory cell blocks, bit line sense amplifier blocks, and control circuit connected to bit line sense amplifier blocks to control constant levels of currents supplied to sensing driving voltage lines
US10658014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Mar 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes memory cell blocks, bit line sense amplifier blocks, and a control circuit connected to one or more of the bit line sense amplifier blocks arranged between the memory cell blocks. The control circuit controls levels of currents respectively supplied to a first sensing driving voltage line and a second sensing driving voltage line driving bit line sense-amplifiers, to be constant. A first sensing driving control signal and/or a second sensing driving control signal, output from the sensing-matching control circuit is provided to the bit line sense amplifiers in all of the bit line sense amplifier blocks, so that the bit line sense amplifiers are constantly driven based on the constant levels of currents supplied to the first sensing driving voltage line and the second sensing driving voltage line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.